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rev. 1.0 / aug. 2012 1 240pin ddr3 sdram vl p registered dimm *sk hynix reserves the right to change pr oducts or specifications without notice. ddr3 sdram vlp registered dimm based on 2gb c-die hmt325v7cfr8c hmt351v7cfr8c hmt351v7cfr4c hmt41gv7cmr8c hmt41gv7cmr4c
rev. 1.0 / aug. 2012 2 revision history revision no. history draft date remark 0.1 initial release aug.2011 0.2 collected : 1866 speed bin table update sep.2011 1.0 latest jedec spec and module line-up update aug.2012
rev. 1.0 / aug. 2012 3 description sk hynix vlp (very low profile) registered ddr3 sd ram dimms (registered double data rate synchro- nous dram dual in-line memory modules) are low po wer, high-speed operation memory modules that use ddr3 sdram devices. these registered sdram dimm s are intended for use as main memory when installed in systems such as servers and workstations. features ? power supply: vdd=1.5v (1.425v to 1.575v) ? vddq = 1.5v (1.425v to 1.575v) ? vddspd=3.0v to 3.6v ? functionality and operations comply with the ddr3 sdram datasheet ? 8 internal banks ? data transfer rates: pc3-14900, pc 3-12800, pc3-10600 ? bi-directional differential data strobe ? 8 bit pre-fetch ? burst length (bl) switch on-the-fly bl8 or bc4(burst chop) ? supports ecc error correction and detection ? on-die termination (odt) ? temperature sensor with integrated spd ? this product is in compliance with the rohs directive. ordering information * in order to uninstall fdhs, pl ease contact sales administrator part number density organization component composition # of ranks fdhs hmt325v7cfr8c-h9/pb/rd 2gb 256mx72 256mx8(h5tq2g83cfr)*9 1 x hmt351v7cfr8c-h9/pb/rd 4gb 512 mx72 256mx8(h5tq2g83cfr)*18 2 x HMT351V7CFR4C-H9/pb/rd 4gb 512 mx72 512mx4(h5tq2g43cfr)*18 1 x hmt41gv7cmr8c-h9/pb 8gb 1gx72 ddp 512mx8(h5tq4g83cmr)*18 4 o hmt41gv7cmr4c-h9/pb 8gb 1gx72 ddp 1gx4(h5tq4g43cmr)*18 2 o
rev. 1.0 / aug. 2012 4 key parameters * sk hynix dram devices support optional downbinning to cl11, cl9 and cl7. spd setting is programmed to match. speed grade address table mt/s grade tck (ns) cas latency (tck) trcd (ns) trp (ns) tras (ns) trc (ns) cl-trcd-trp ddr3-1333 -h9 1.5 9 13.5 (13.125)* 13.5 (13.125)* 36 49.5 (49.125)* 9-9-9 ddr3-1600 -pb 1.25 11 13.75 (13.125)* 13.75 (13.125)* 35 48.75 (49.125)* 11-11-11 ddr3-1866 -rd 1.07 13 13.91 (13.125)* 13.91 (13.125)* 34 47.91 (49.125)* 13-13-13 grade frequency [mhz] remark cl6 cl7 cl8 cl9 cl10 cl11 cl12 cl13 -h9 800 1066 1066 1333 1333 -pb 800 1066 1066 1333 1333 1600 -rd 800 1066 1066 1333 1333 1600 1866 2gb(1rx8) 4gb(2rx8) 4gb(1rx4) 8gb(4rx8) 8gb(2rx4) refresh method 8k/64ms 8k/64ms 8k/64ms 8k/64ms 8k/64ms row address a0-a14 a0-a14 a0-a14 a0-a14 a0-a14 column address a0-a9 a0-a9 a0-a9, a11 a0-a9 a0-a9, a11 bank address ba0-ba2 ba0-ba2 ba0-ba2 ba0-ba2 ba0-ba2 page size 1kb 1kb 1kb 1kb 1kb
rev. 1.0 / aug. 2012 5 pin descriptions pin name description num ber pin name description num ber ck0 clock input, positive line 1 odt[1:0] on die termination inputs 2 ck0 clock input, negative line 1 dq[63:0] data input/output 64 ck1 clock input, positive line 1 cb[ 7:0] data check bits input/output 8 ck1 clock input, negative lin e 1 dqs[8:0] data strobes 9 cke[1:0] clock enables 2 dqs[8:0] data strobes, negative line 9 ras row address strobe 1 dm[8:0]/ dqs[17:9], tdqs[17:9] data masks / data strobes, termination data strobes 9 cas column address strobe 1 dqs[17:9] , tdqs[17:9] data strobes, negative line, termination data strobes 9 we write enable 1 event reserved for optional hardware temperature sensing 1 s [3:0] chip selects 4 test memory bus test tool (not con- nected and not usable on dimms) 1 a[9:0],a11, a[15:13] address inputs 14 reset register and sdram control pin 1 a10/ap address input/autoprecharge 1 v dd power supply 22 a12/bc address input/burst chop 1 v ss ground 59 ba[2:0] sdram bank addresses 3 v refdq reference voltage for dq 1 scl serial presence detect (spd) clock input 1 v refca reference voltage for ca 1 sda spd data input/output 1 v tt termination voltage 4 sa[2:0] spd address inputs 3 v ddspd spd power 1 par_in parity bit for the address and control bus 1 err_out parity error found on the address and control bus 1
rev. 1.0 / aug. 2012 6 input/output functional descriptions symbol type polarity function ck0 in positive line positive line of the differential pair of system clock inputs that drives input to the on- dimm clock driver. ck0 in negative line negative line of the differential pair of system clock inputs that drives the input to the on-dimm clock driver. ck1 in positive line terminated but not used on rdimms. ck1 in negative line terminated but not used on rdimms. cke[1:0] in active high cke high activates, and cke low deactivates internal clock signal s, and device input buffers and output drivers of the sdra ms. taking cke low provides precharge power-down and self refres h operation (all banks idle), or active power down (row active in any bank) s [3:0] in active low enables the command decoders for the asso ciated rank of sdram when low and dis- ables decoders when high. when decoders are disabled, new commands are ignored and previous operations continue. other combinations of these input signals perform unique functions, including disabling all outputs (except cke and odt) of the register(s) on the dimm or accessing internal control words in the register device(s). for modules with two registers, s[3:2] operate similarly to s[1:0] for the second set of register out- puts or register control words. odt[1:0] in active high on-die termination control signals r as , cas , we in active low when sampled at the positive rising edge of the clock, cas , ras , and we define the operation to be executed by the sdram. v refdq supply reference voltage fo r dq0-dq63 and cb0-cb7. v refca supply reference voltage for a0-a15, ba0-ba2, ras , cas , we , s0 , s1 , cke0, cke1, par_in, odt0 and odt1. ba[2:0] in ? selects which sdram bank of eight is activated. ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines mode register is to be accessed during an mrs cycle. a[15:13, 12/bc ,11, 10/ap,[9:0] in ? provided the row address for active commands and the column address and auto precharge bit for read/write commands to select one location out of the mem- ory array in the respective bank. a10 is sampled during a precharge command to deter- mine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba. a12 is also utilized for bl 4/8 identification for ??bl on the fly?? during cas command. the address inputs also pro- vide the op-code during mode register set commands. dq[63:0], cb[7:0] i/o ? data and check bi t input/output pins dm[8:0] in active high masks write data when high, issued concurrently with input data. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic. v tt supply termination voltage for address/command/control/clock nets.
rev. 1.0 / aug. 2012 7 dqs[17:0] i/o positive edge positive line of the differential data strobe for input and output data. dqs[17:0] i/o negative edge negative line of the differential data strobe for input and output data. tdqs[17:9] tdqs[17:9] out tdqs/tdqs is applicable for x8 drams only. when enabled via mode register a11=1 in mr1,dram will enable the same termination resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode regist er a11=0 in mr1, dm/tdqs will provide the data mask function and tdqs is not used. x4 drams must disable the tdqs function via mode register a11=0 in mr1 sa[2:0] in ? these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. sda i/o ? this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v ddspd on the system pl anar to act as a pullup. scl in ? this signal is used to clock data into and out of the spd eeprom. a resistor may be con- nected from the scl bus time to v ddspd on the system planar to act as a pullup. event out (open drain) active low this signal indicates that a thermal event has been detected in the thermal sensing device.the system should guarantee the electrical level requirement is met for the event pin on ts/spd part. no pull-up resister is provided on dimm. v ddspd supply serial eeprom positive power supply wired to a separate power pin at the connector which supports from 3.0 volt to 3.6 volt (nominal 3.3v) operation. reset in the reset pin is connected to the reset pin on the register and to the reset pin on the dram. par_in in parity bit for the address and control bus. (?1 ?: odd, ?0 ?: even) err_out out (open drain) parity error detected on the address and cont rol bus. a resistor may be connected from err_out bus line to v dd on the system planar to act as a pull up. test used by memory bus analysis tools (unused (nc) on memory dimms) symbol type polarity function
rev. 1.0 / aug. 2012 8 pin assignments pin # front side (left 1?60) pin # back side (right 121?180) pin # front side (left 61?120) pin # back side (right 181?240) 1v ref dq 121 v ss 61 a2 181 a1 2 v ss 122 dq4 62 v dd 182 v dd 3 dq0 123 dq5 63 nc, ck1 183 v dd 4 dq1 124 v ss 64 nc, ck1 184 ck0 5 v ss 125 dm0,dqs9, tdqs9 65 v dd 185 ck0 6dqs0 126 nc,dqs9 , tdqs9 66 v dd 186 v dd 7 dqs0 127 v ss 67 v ref ca 187 event , nc 8 v ss 128 dq6 68 par_in, nc 188 a0 9 dq2 129 dq7 69 v dd 189 v dd 10 dq3 130 v ss 70 a10 / ap 190 ba1 11 v ss 131 dq12 71 ba0 191 v dd 12 dq8 132 dq13 72 v dd 192 ras 13 dq9 133 v ss 73 we 193 s0 14 v ss 134 dm1,dqs10, tdqs10 74 cas 194 v dd 15 dqs1 135 nc,dqs10 , tdqs10 75 v dd 195 odt0 16 dqs1 136 v ss 76 s1 , nc 196 a13 17 v ss 137 dq14 77 odt1, nc 197 v dd 18 dq10 138 dq15 78 v dd 198 s3 , nc 19 dq11 139 v ss 79 s2 , nc 199 v ss 20 v ss 140 dq20 80 v ss 200 dq36 21 dq16 141 dq21 81 dq32 201 dq37 22 dq17 142 v ss 82 dq33 202 v ss 23 v ss 143 dm2,dqs11, tdqs11 83 v ss 203 dm4,dqs13, tdqs13 24 dqs2 144 nc,dqs11 , tdqs11 84 dqs4 204 nc,dqs13 , tdqs13 25 dqs2 145 v ss 85 dqs4 205 v ss 26 v ss 146 dq22 86 v ss 206 dq38 27 dq18 147 dq23 87 dq34 207 dq39 28 dq19 148 v ss 88 dq35 208 v ss 29 v ss 149 dq28 89 v ss 209 dq44 30 dq24 150 dq29 90 dq40 210 dq45 31 dq25 151 v ss 91 dq41 211 v ss nc = no connect; rfu = reserved future use
rev. 1.0 / aug. 2012 9 32 v ss 152 dm3,dqs12, tdqs12 92 v ss 212 dm5,dqs14, tdqs14 33 dqs3 153 nc,dqs12 , tdqs12 93 dqs5 213 nc,dqs14 , tdqs14 34 dqs3 154 v ss 94 dqs5 214 v ss 35 v ss 155 dq30 95 v ss 215 dq46 36 dq26 156 dq31 96 dq42 216 dq47 37 dq27 157 v ss 97 dq43 217 v ss 38 v ss 158 cb4, nc 98 v ss 218 dq52 39 cb0, nc 159 cb5, nc 99 dq48 219 dq53 40 cb1, nc 160 v ss 100 dq49 220 v ss 41 v ss 161 nc,dm8,dqs17, tdqs17 101 v ss 221 dm6,dqs15, tdqs15 42 dqs8 162 nc,dqs17 , tdqs17 102 dqs6 222 nc,dqs15 , tdqs15 43 dqs8 163 v ss 103 dqs6 223 v ss 44 v ss 164 cb6, nc 104 v ss 224 dq54 45 cb2, nc 165 cb7, nc 105 dq50 225 dq55 46 cb3, nc 166 v ss 106 dq51 226 v ss 47 v ss 167 nc(test) 107 v ss 227 dq60 48 vtt, nc 168 reset 108 dq56 228 dq61 key key 109 dq57 229 v ss 49 vtt, nc 169 cke1, nc 110 v ss 230 dm7,dqs16, tdqs16 50 cke0 170 v dd 111 dqs7 231 nc,dqs16 , tdqs16 51 v dd 171 a15 112 dqs7 232 v ss 52 ba2 172 a14 113 v ss 233 dq62 53 err_out , nc 173 v dd 114 dq58 234 dq63 54 v dd 174 a12 / bc 115 dq59 235 v ss 55 a11 175 a9 116 v ss 236 v ddspd 56 a7 176 v dd 117 sa0 237 sa1 57 v dd 177 a8 118 scl 238 sda 58 a5 178 a6 119 sa2 239 v ss 59 a4 179 v dd 120 v tt 240 v tt 60 v dd 180 a3 pin # front side (left 1?60) pin # back side (right 121?180) pin # front side (left 61?120) pin # back side (right 181?240) nc = no connect; rfu = reserved future use
rev. 1.0 / aug. 2012 10 registering clock driver specifications capacitance values input & output timing requirements symbol parameter conditions min typ max unit c i input capacitance, data inputs 1.5 - 2.5 pf input capacitance, ck, ck , fbin, fbin (up to ddr3-1600) 1.5 - 2.5 pf c ir input capacitance, reset , mirror, qcsen v i = v dd or gnd; v dd = 1.5v --3pf symbol parameter conditions ddr3-800 1066/1333 ddr3-1600 ddr3-1866 unit min max min max min max f clock input clock fre- quency application fre- quency 300 670 300 810 300 945 mhz f test input clock fre- quency test frequency 70 300 70 300 70 300 mhz t su setup time input valid before ck/ck 100 - 50 - 40 - ps t h hold time input to remain valid after ck/ck 175-125- 75 -ps t pdm propagation delay, single-bit switching ck/ck to output 0.65 1.0 0.65 1.0 0.65 1.0 ns t dis output disable time (1/2-clock prelaunch) yn/yn to output float 0.5 + tqsk1(min) - 0.5 + tqsk1(min) - 0.5 + tqsk1(min) -ps t en output enable time (1/2-clock prelaunch) output driving to yn/yn 0.5 - tqsk1(max) - 0.5 - tqsk1(max) - 0.5 - tqsk1(max) -ps
rev. 1.0 / aug. 2012 11 on dimm thermal sensor the ddr3 sdram dimm temperature is monitored by in tegrated thermal sensor. the integrated thermal sensor comply with jedec ?tse2002av, serial presence detect with temperature sensor?. connection of thermal sensor temperature-to-digital conversion performance parameter condition min typ max unit temperature sensor accuracy (grade b) active range, 75c < t a < 95c - 0.5 1.0 c monitor range, 40c < t a < 125c - 1.0 2.0 c -20c < t a < 125c - 2.0 3.0 c resolution 0.25 c event scl sda sa0 sa1 sa2 event scl sda sa0 sa1 sa2 spd with integrated ts
rev. 1.0 / aug. 2012 12 functional block diagram 2gb, 256mx72 modu le(1rank of x8) cb[7:0] dqs8_t dqs8_c dm8/dqs17_t dqs17_c rrasa_n rcasa_n rs0a_n rwea_n pck0a_t pck0a_c rcke0a rodt0a a[n:o]a vtt dq[31:24] dqs3_t dqs3_c dm3/dqs12_t dqs12_c dq[23:16] dqs2_t dqs2_c dm2/dqs11_t dqs11_c dq[15:8] dqs1_t dqs1_c dm1/dqs10_t dqs10_c dq[7:0] dqs 0 _t dqs 0 _c dm 0 /dqs9_t dqs9_c dqs_t dqs_c tdqs_t tdqs_c d8 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d3 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a[o:n]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d2 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a[o:n]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d1 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d0 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a [n :o]/ba[n:o] dq[39:32] dqs4_t dqs4_c dm4/dqs13_t dqs13_c rrasb_n rcasb_n rs0b_n rweb_n pck0b_t pck0b_c rcke0b rodt0b a[n:o]b vtt dq[47:40] dqs5_t dqs5_c dm5/dqs14_t dqs14_c dq[55:48] dqs6_t dqs6_c dm6/dqs15-t dqs15_c dq[63:56] dqs7_t dqs7_c dm7/dqs16_t dqs16_c dqs_t dqs_c tdqs_t tdqs_c d4 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a[o:n]/ba[o:n] dqs_t dqs_c tdqs_t tdqs_c d5 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a[o:n]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d6 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a[o:n]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d7 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_n cke odt a[n:o]/ba[n:o] /ba[n:o]a /ba[n:o]b s0_n s1_n ba[n:0] a[n:0] ras_n cas_n we_n cke0 odt0 ck0_t ck0_c par_in rs0a_n cs0_n: sdrams d[3:0], d8 rs0bck_n cs0_n: sdrams d[7:4] rba[n:0]a ba[n:0]: sdrams d[3:0], d8 rrasb_n ras_n: sdrams d[7:4] rba[n:0]b ba[n:0]: sdrams d[7:4] ra[n:0]b a[n:0]: sdrams d[7:4] ra[n:0]a a[n:0]: sdrams d[3:0], d8 rrasa_n ras_n: sdrams d[3:0], d8 rcasb_n cas_n: sdrams d[7:4] rcasa_n cas_n: sdrams d[3:0], d8 rweb_n we_n: sdrams d[7:4] rwea_n we_n: sdrams d[3:0], d8 rcke0b cke0: sdrams d[7:4] rcke0a cke0: sdrams d[3:0], d8 rodt0b odt0: sdrams d[7:4] rodt0a odt0: sdrams d[3:0], d8 pck0b_t ck_t: sdrams d[7:4] pck0a_t ck_t: sdrams d[3:0], d8 pck0b_c ck_c: sdrams d[7:4] pck0a_c ck_c: sdrams d[3:0], d8 err_out_n oerr_n reset_n rst_n rst_n: sdrams d[8:0] s[3:2], cke1, odt1, are nc (unused regist er inputs odt1 and cke1 have a 120...330 ? resistor to ground 1: 2 r e g i s t e r / p d0?d8 v dd v tt v ddspd d0?d8 vrefdq spd vrefca v ss d0?d8 d0?d8 note: 1.dq-to-i/o wiring may be changed within byte. 2.zq resistors are 240 ? 1%.for all other resistor values refer to the appropriate wiring diagram. vddspd event scl sda sa0 spd with integrated ts sa1 sa2 vss vddspd event scl sda sa0 sa1 sa2 vss plan to use spd with integrated ts of class b and might be changed on customer?s requests. for more details of spd and thermal sensor, please contact local sk hynix sales representative 120 ? 1% ck1_t ck1_c 120 ? 1% l l
rev. 1.0 / aug. 2012 13 4gb, 512mx72 module(2 rank of x8) - page1 dqs_t dqs_c tdqs_t tdqs_c d17 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] rrasa_n rcasa_n rs0a_n rwea_n pck0a_t pck0a_c rcke0a rodt0a a[n:o]a vtt /ba[n:o]a rs1a_c pck1a_t pck1a_c rcke1a rodt1a dq[31:24] dqs3_t dqs3_c dm3/dqs12_t dqs12_c dqs_t dqs_c tdqs_t tdqs_c d3 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d12 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[23:16] dqs2_t dqs2_c dm2/dqs11_t dqs11_c dqs_t dqs_c tdqs_t tdqs_c d2 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d11 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[15:8] dqs1_t dqs1_c dm1/dqs10_t dqs10_c dqs_t dqs_c tdqs_t tdqs_c d1 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[o:n]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d10 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[o:n]/ba[n:o] dq[7:0] dqs0_t dqs0_c dm0/dqs9_t dqs9_c dqs_t dqs_c tdqs_t tdqs_c d0 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d9 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] cb[7:0] dqs8_t dqs8_c dm8/dqs17_t dqs17_c dqs_t dqs_c tdqs_t tdqs_c d8 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d13 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] rrasb rcasb rs0b rweb pck0b pck0b rcke0b rodt0b a[n:o]b vtt /ba[n:o]b rs1b pck1b pck1b rcke1b rodt1b dq[47:40] dqs5_t dqs5_c dm5/dqs14_t dqs14_ dqs_t dqs_c tdqs_t tdqs_c d5 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d14 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq55:48] dqs6_t dqs6_c dm6/dqs15_t dqs15_c dqs_t dqs_c tdqs_t tdqs_c d6 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d15 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[63:56] dqs7_t dqs7_c dm7/dqs16_t dqs16_c dqs_t dqs_c tdqs_t tdqs_c d7 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dqs_t dqs_c tdqs_t tdqs_c d16 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[o:n]/ba[n:o] dq[39:32] dqs4_t dqs4_c dm4/dqs13-t dqs13_c dqs_t dqs_c tdqs_t tdqs_c d4 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] d0?d17 v dd d0?d17 v tt v ddspd d0?d17 vrefdq serial pd vrefca v ss d0?d17 d0?d17 note: 1. dq-to-i/o wiring may be changed within a byte. 2. unless otherwise noted, resistor values are 15 ?5 %. 3. zq resistors are 240 ?1 %. for all other resistor values refer to the appropriate wiring diagram. 4. see the wiring diagrams for al l resistors associated with the command, address and control bus. vddspd event scl sda sa0 spd with integrated ts sa1 sa2 vss vddspd event_n scl sda sa0 sa1 sa2 vss plan to use spd with integrated ts of class b and might be changed on customer?s requests. for more details of spd and thermal sensor, please contact local sk hynix sales representative
rev. 1.0 / aug. 2012 14 4gb, 512mx72 module(2 rank of x8) - page2 s0_n s1_n ba[n:0] a[n:0] ras_n cas_n we_n cke0 odt0 ck0_t ck0_c par_in rs0a_n cs0_n: sdrams d[3:0], d8 rs0b_n cs0_n: sdrams d[7:4] rrasb_n ras_n: sdrams d[7:4], d[16:13] rba[n:0]b ba[n:0]: sdrams d[7:4], d[16:13] rba[n:0]a ba[n:0]: sdrams d[3:0], d[12:8], d17 rrasa_n ras_n: sdrams d[3:0], d[12:8], d17 rcasb_n cas_n: sdrams d[7:4], d[16:13] rcasa_n cas_n: sdrams d[3:0], d[12:8], d17 rweb_n we_n: sdrams d[7:4], d[16:13] rwea_n we_n: sdrams d[3:0], d[12:8], d17 rcke0b cke0: sdrams d[7:4] rcke0a cke0: sdrams d[3:0], d8 rodt0b odt0: sdrams d[7:4] rodt0a odt0: sdrams d[3:0], d8 pck0b_t ck_t: sdrams d[7:4] pck0a_t ck-t: sdrams d[3:0], d8 pck0b_c ck_c: sdrams d[7:4] pck0a_c ck_c: sdrams d[3:0], d8 err_out_n reset_n rst_n rst_n: sdrams d[17:0] 1:2 r e g i s t e r / p ra[n:0]b a[n:0]: sdrams d[7:4], d[16:13] ra[n:0]a a[n:0]: sdrams d[3:0], d[12:8], d17 l l s[3:2] nc 120 ? ck1_t ck1_c 120 ?
rev. 1.0 / aug. 2012 15 4gb, 512mx72 module(1 rank of x4) - page1 rrasa_n rcasa_n rs0a_n rwea_n pck0a_t pck0a_c rcke0a rodt0a a[n:o]a vtt /ba[n:o]a cb[3:0] dqs8_t dqs8_c dqs_t dqs_c dm d8 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] cb[7:4] dqs17_t dqs17_c vss dqs_t dqs_c dm d17 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss dq[27:24] dqs3_t dqs3_c dqs_t dqs_c dm d3 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[31:28] dqs12_t dqs12_c vss dqs_t dqs_c dm d12 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss dq[19:16] dqs2_t dqs2_c dqs_t dqs_c dm d2 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq23:20] dqs11_t dqs11_c vss dqs_t dqs_c dm d11 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss dq[11;8] dqs1_t dqs1_c dqs_t dqs_c dm d1 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[15:12] dqs10_t dqs10_c vss dqs_t dqs_c dm d10 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss dq[3:0] dqs0_t dqs0_c dqs_t dqs_c dm d0 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[7:4] dqs9_t dqs9_c vss dqs_t dqs_c dm d9 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss rrasb_n rcasb_n rs0b_n rweb_n pck0b_t pck0b_c rcke0b rodt0b a[o:n]b vtt /ba[o:n]b dq[35:32] dqs4_t dqs4_c dqs_t dqs_c dm d4 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[39:36] dqs13_t dqs13_c vss dqs_t dqs_c dm d13 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss dq[43:40] dqs5_t dqs5_c dqs_t dqs_c dm d5 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[47:44] dqs14_t dqs14_c vss dqs_t dqs_c dm d14 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss dq[51:48] dqs6_t dqs6_c dqs_t dqs_c dm d6 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[55;52] dqs15_t dqs15_c vss dqs_t dqs_c dm d15 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss dq[59:56] dqs7_t dqs7_c dqs_t dqs_c dm d7 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] dq[63:60] dqs16_t dqs16_c vss dqs_t dqs_c dm d16 dq [3:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:o] vss vss vss d0?d17 v dd v tt v ddspd d0?d17 vrefdq spd vrefca v ss d0?d17 d0?d17 note: 1. dq-to-i/o wiring may be changed within a nibble. 2. unless otherwise noted, resistor values are 15 %. 3. see the wiring diagrams for all resistors associated with the com- mand, address and control bus. 4. zq resistors are 240 %. for all other resistor values refer to the appropriate wiring diagram. 1 ? ? 5 ? vddspd event scl sda sa0 spd with integrated ts sa1 sa2 vss vddspd event scl sda sa0 sa1 sa2 vss plan to use spd with integrated ts of class b and might be changed on customer?s requests. for more details of spd and thermal sensor, please contact local sk hynix sales representative ?
rev. 1.0 / aug. 2012 16 4gb, 512mx72 module(1 rank of x4) - page2 ? * s[3:2]_n are nc (note: otherwise stated differently all resistors values on this base are 22 +-5%) ? s0_n s1_n ba[2:0] a[15:0] ras_n cas_n we_n cke[1:0] odt[1:0] ck0_t ck0_c par_in rs0a_n cs0a_n: sdrams d[3:0], d8, d[12:9], d17 rs1a_n cs1a_n: sdrams d[21:18], d26, d[30:27], d35 rrasb_n ras_n: sdrams d[7:4], d[16:13], d[25:22], d[34:31] rba[2:0]b ba[2:0]: sdrams d[7:4], d[16:13], d[25:22], d[34:31] rba[2:0]a ba[2:0]: sdrams d[3:0], d8, d[12:9], d17, d[21:18], d26, d[30:27], d35 rrasa_n ras_n: sdrams d[3:0], d8, d[12:9], d17, d[21:18], d26, d[30:27], d35 rcasb_n cas_n: sdrams d[7:4], d[16:13], d[25:22], d[34:31] rcasa_n cas_n: sdrams d[3:0], d8, d[12:9], d17, d[21:18], d26, d[30:27], d35 rweb_n we_n: sdrams d[7:4], d[16:13], d[25:22], d[34:31] rwea_n we_n: sdrams d[3:0], d8, d[12:9], d17, d[21:18], d26, d[30:27], d35 rcke0b cke[1:0]b_n: sdrams d[21 :18], d26, d[30:27], d35 rcke0a cke[1:0]a_n: sdrams d[3:0], d8. d[12:9], d17 rodt[1:0]b odt0: sdrams d[21:18] , d26, d[30:27], d35 rodt[1:0]a odt0: sdrams d[3:0] , d8. d[12:9], d17 ck0b_t_r0 ck_t: sdrams d[7:4], d[25:22] ck0a_t_r0 ck-t: sdrams d[3:0], d8, d[21:18], d26 ck0b_c _r0 ck_c: sdrams d[7:4], d[25:22] ck0a_c _r0 ck_c: sdrams d[3:0], d8, d[21:18], d26 err_out_n reset_n rst_n rst_n: all sdrams 1:2 r e g i s t e r / p ra[15:0]b a[15:0]: sdrams d[7:4], d[ 16:13], d[25:22], d[34:31] ra[15:0]a a[15:0]: sdrams d[3:0], d8, d[12:9], d17, d[21:18], d26, d[30:27], d35 l l 120 ? ck1_t ck1_c 120 ? rs0b_n cs0b_n: sdrams d[7:4], d[16:13] rs1b_n cs1b_n: sdrams d[25:22], d[34:31] ck0b_t_r1 ck_t: sdrams d[16:13], d[34:31] ck0a_t_r1 ck-t: sdrams d[12:9], d17, d[30:27], d35 ck0b_c _r1 ck_c: sdrams d[16:13], d[34:31] ck0a_c _r1 ck_c: sdrams d[12:9], d17, d[30:27], d35
rev. 1.0 / aug. 2012 17 8gb, 1gx72 module(4ra nk of x8) - page1 vss vss vss rrasa_n rcasa_n rs0_n rwea_n pck0a_t pck0a_c rcke0a rodt0a ra[n:0]a vtt /rba[n:0]a cb[7:0] dqs8_t dqs8_c dm8/tdqs17_t tdqs17_c dqs dqs tdqs tdqs d17 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] rs1_n rcke1a vdd dqs dqs tdqs tdqs d8 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] rs2_n pck1a_t pck1a_c rodt1a dqs dqs tdqs tdqs d35 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] rs3_n vdd dqs dqs tdqs tdqs d26 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss vss vss vss dq[31:24] dqs3_t dqs3_c dm3/tdqs12_t tdqs12_c dqs dqs tdqs tdqs d12 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d3 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d30 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d21 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss vss vss vss dq[23:16] dqs2_t dqs2_c dm2/tdqs11_t tdqs11_c dqs dqs tdqs tdqs d11 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d2 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d29 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d20 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss vss vss vss dq[15:8] dqs1_t dqs1_c dm1/tdqs10_t tdqs10_c dqs dqs tdqs tdqs d10 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d1 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d28 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d19 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss vss vss vss dq[7:0] dqs0_t dqs0_c dm0/tdqs9_t tdqs9_c dqs dqs tdqs tdqs d9 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d0 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d27 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d18 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss
rev. 1.0 / aug. 2012 18 8gb, 1gx72 module(4ra nk of x8) - page2 d0-d35 v dd v tt v ddspd d0-d35 v refdq serial pd v refca v ss d0-d35 d0-d35 vddspd event scl sda sa0 spd with integrated ts sa1 sa2 vss vddspd event scl sda sa0 sa1 sa2 vss plan to use spd with integrated ts of class b and might be changed on customer?s requests. for more details of spd and thermal sensor, please contact local sk hynix sales representative vss vss vss rrasa_n rcasa_n rs0_n rwea_n pck0a_t pck0a_c rcke0a rodt0a ra[n:0]a vtt /rba[n:0]a dq[39:32] dqs4_t dqs4_c dm4/tdqs13_t tdqs13_c dqs dqs tdqs tdqs d13 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] rs1_n rcke1a vdd dqs dqs tdqs tdqs d4 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] rs2_n pck1a_t pck1a_c rodt1a dqs dqs tdqs tdqs d31 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] rs3_n vdd dqs dqs tdqs tdqs d22 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss vss vss vss dq[47:40] dqs5_t dqs5_c dm5/tdqs14_t tdqs14_c dqs dqs tdqs tdqs d14 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d5 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d32 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d23 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss vss vss vss dq[55:48] dqs6_t dqs6_c dm6/tdqs15_t tdqs15_c dqs dqs tdqs tdqs d15 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d6 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d33 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d24 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss vss vss vss dq[63:56] dqs7_t dqs7_c dm7/tdqs16_t tdqs16_c dqs dqs tdqs tdqs d16 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d7 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d34 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] dqs dqs tdqs tdqs d25 dq [7:0] zq ras_n cas_n cs_n we_n ck_t ck_c cke odt a[n:o]/ba[n:0] vss note: 1. dq-to-i/o wiring may be changed within a nibble. 2. unless otherwise noted, resistor values are 15 %. 3. see the wiring diagrams for all resistors associated with the com- mand, address and control bus. 4. zq resistors are 240 %. for all other resistor values refer to the appropriate wiring diagram. 1 ? ? 5 ? ?
rev. 1.0 / aug. 2012 19 8gb, 1gx72 module(4ra nk of x8) - page3 s0_n s1_n ba[n:0] a[n:0] ras_n cas_n we_n cke0 odt0 ck0_t ck0_c par_in rs0_n cs1_n: sdrams d[17:9] rs1_n cs0_n: sdrams d[8:0] rs2_n cs1_n: sdrams d[35:27] rrasb_n ras_n: sdrams d[7:4], d[ 16:13], u[25:22], u[34:31] rs3_n cs0_n: sdrams d[26:18] rba[n:0]b ba[n:0]: sdrams d[7:4], d[16:13], u[25:22], u[34:31] rba[n:0]a ba[n:0]: sdrams d[3:0], d[12:8], d[21:17], d[30:26], d35 rrasa_n ras_n: sdrams d[3:0], d[12 :8], d[21:17], d[30:26], d35 rcasb_n cas_n: sdrams d[7:4], d[ 16:13], u[25:22], u[34:31] rcasa_n cas_n: sdrams d[3:0], d[12:8], d[21:17], d[30:26], d35 rweb_n we_n: sdrams d[7:4], d[16:13], u[25:22], u[34:31] rwea_n we_n: sdrams d[3:0], d[12:8 ], d[21:17], d[30:26], d35 rcke0 b cke1: sdrams d[16:13], d[34:31] rcke0 a cke1: sdrams d[12:9], d17, d[30:27], d35 rodt0b odt1: sdrams d[16:13] rodt0a odt1: sdrams d[12:9], d17 pck0b_t ck_t: sdrams d[7:4], d[16:13] pck0a_t ck_t: sdrams d[3:0], d[12:8], d17 pck0b_c ck_c: sdrams d[7:4], d[16:13] pck0a_c ck_c: sdrams d[3:0], d[12:8], d17 err_out_n reset_n rst_n reset_n: sdrams d[35:0] 1:2 r e g i s t e r / p rcke1b cke0: sdrams d[7:4], d[25:22] rcke1 a cke0: sdrams d[3:0], d8, d[21:18], d26 odt1 rodt1b odt1: sdrams d[34:31] rodt1a odt1: sdrams d[30:27], d35 cke1 ra[n:0]b a[n:0]: sdrams d[7:4], d[ 16:13], u[25:22], u[34:31] ra[n:0]a a[n:0]: sdrams d[3:0], d[12 :8], d[21:17], d[30:26], d35 pck1b_t ck_t: sdrams d[25:22], d[34:31] pck1a_t ck_t: sdrams d[21:18], d[30:26], d35 pck1b_c ck_c: sdrams d[25:22], d[34:31] pck1a_c ck_c: sdrams d[21:18], d[30:26], d35 l l ck1_t ck1_c 120 ? s2_n s3_n 120 ?
rev. 1.0 / aug. 2012 20 8gb, 1gx72 module(2ra nk of x4) - page1 dq[3:0] dqs0_t dqs0_c dqs_t dqs_c d0 dq [3:0] dm cs_n zq vss dqs_t dqs_c d18 dq [3:0] dm cs_n zq vss dq[7:4] dqs9_t dqs9_c dqs_t dqs_c d9 dq [3:0] dm cs_n zq vss dqs_t dqs_c d27 dq [3:0] dm cs_n zq vss dq[11:8] dqs1_t dqs1_c dqs_t dqs_c d1 dq [3:0] dm cs_n zq vss dqs_t dqs_c d19 dq [3:0] dm cs_n zq vss dq[12:15] dqs10_t dqs10_c dqs_t dqs_c d10 dq [3:0] dm cs_n zq vss dqs_t dqs_c d28 dq [3:0] dm cs_n zq vss dq[16:19] dqs2_t dqs2_c dqs_t dqs_c d2 dq [3:0] dm cs_n zq vss dqs_t dqs_c d20 dq [3:0] dm cs_n zq vss dq[20:23] dqs11_t dqs11_c dqs_t dqs_c d11 dq [3:0] dm cs_n zq vss dqs_t dqs_c d29 dq [3:0] dm cs_n zq vss dq[24:27] dqs3_t dqs3_c dqs_t dqs_c d3 dq [3:0] dm cs_n zq vss dqs_t dqs_c d21 dq [3:0] dm cs_n zq vss dq[28:31] dqs12_t dqs12_c dqs_t dqs_c d12 dq [3:0] dm cs_n zq vss dqs_t dqs_c d30 dq [3:0] dm cs_n zq vss dq[32:35] dqs4_t dqs4_c dqs_t dqs_c d4 dq [3:0] dm cs_n zq vss dqs_t dqs_c d22 dq [3:0] dm cs_n zq vss dq[36:39] dqs13_t dqs13_c dqs_t dqs_c d13 dq [3:0] dm cs_n zq vss dqs_t dqs_c d31 dq [3:0] dm cs_n zq vss dq[40:43] dqs5_t dqs5_c dqs_t dqs_c d5 dq [3:0] dm cs_n zq vss dqs_t dqs_c d23 dq [3:0] dm cs_n zq vss dq[44:47] dqs14_t dqs14_c dqs_t dqs_c d14 dq [3:0] dm cs_n zq vss dqs_t dqs_c d32 dq [3:0] dm cs_n zq vss dq[48:51] dqs6_t dqs6_c dqs_t dqs_c d6 dq [3:0] dm cs_n zq vss dqs_t dqs_c d24 dq [3:0] dm cs_n zq vss dq[52:55] dqs15_t dqs15_c dqs_t dqs_c d15 dq [3:0] dm cs_n zq vss dqs_t dqs_c d33 dq [3:0] dm cs_n zq vss dq[56:59] dqs7_t dqs7_c dqs_t dqs_c d7 dq [3:0] dm cs_n zq vss dqs_t dqs_c d25 dq [3:0] dm cs_n zq vss dq[60:63] dqs16_t dqs16_c dqs_t dqs_c d16 dq [3:0] dm cs_n zq vss dqs_t dqs_c d34 dq [3:0] dm cs_n zq vss cb[3:0] dqs8_t dqs8_c dqs_t dqs_c d8 dq [3:0] dm cs_n zq vss dqs_t dqs_c d26 dq [3:0] dm cs_n zq vss cb[7:4] dqs17_t dqs17_c dqs_t dqs_c d17 dq [3:0] dm cs_n zq vss dqs_t dqs_c d35 dq [3:0] dm cs_n zq vss vss rs0_n rs1_n d0?d17 v dd v tt v ddspd d0?d17 vrefdq spd vrefca v ss d0?d17 d0?d17 note: 1. dq-to-i/o wiring may be changed within a nibble. 2. zq pins of each sdram are connected to individual rzq resistors (240+/-1%) ohms. vddspd event scl sda sa0 spd with integrated ts sa1 sa2 vss vddspd event scl sda sa0 sa1 sa2 vss plan to use spd with integrated ts of class b and might be changed on customer?s requests. for more details of spd and thermal sensor, please contact local sk hynix sales representative
rev. 1.0 / aug. 2012 21 8gb, 1gx72 module(2ra nk of x4) - page2 s0_n s1_n ba[n:0] a[n:0] ras_n cas_n we_n cke0 odt0 ck0_t ck0_c par_in rs0_n cs1_n: sdrams d[17:9] rs1_n cs0_n: sdrams d[8:0] rs2_n cs1_n: sdrams d[35:27] rrasb_n ras_n: sdrams d[7:4], d[ 16:13], u[25:22], u[34:31] rs3_n cs0_n: sdrams d[26:18] rba[n:0]b ba[n:0]: sdrams d[7:4], d[16:13], u[25:22], u[34:31] rba[n:0]a ba[n:0]: sdrams d[3:0], d[12:8], d[21:17], d[30:26], d35 rrasa_n ras_n: sdrams d[3:0], d[12 :8], d[21:17], d[30:26], d35 rcasb_n cas_n: sdrams d[7:4], d[ 16:13], u[25:22], u[34:31] rcasa_n cas_n: sdrams d[3:0], d[12:8], d[21:17], d[30:26], d35 rweb_n we_n: sdrams d[7:4], d[16:13], u[25:22], u[34:31] rwea_n we_n: sdrams d[3:0], d[12:8 ], d[21:17], d[30:26], d35 rcke0 b cke1: sdrams d[16:13], d[34:31] rcke0 a cke1: sdrams d[12:9], d17, d[30:27], d35 rodt0b odt1: sdrams d[16:13] rodt0a odt1: sdrams d[12:9], d17 pck0b_t ck_t: sdrams d[7:4], d[16:13] pck0a_t ck_t: sdrams d[3:0], d[12:8], d17 pck0b_c ck_c: sdrams d[7:4], d[16:13] pck0a_c ck_c: sdrams d[3:0], d[12:8], d17 err_out_n reset_n rst_n reset_n: sdrams d[35:0] 1:2 r e g i s t e r / p rcke1b cke0: sdrams d[7:4], d[25:22] rcke1 a cke0: sdrams d[3:0], d8, d[21:18], d26 odt1 rodt1b odt1: sdrams d[34:31] rodt1a odt1: sdrams d[30:27], d35 cke1 ra[n:0]b a[n:0]: sdrams d[7:4], d[ 16:13], u[25:22], u[34:31] ra[n:0]a a[n:0]: sdrams d[3:0], d[12 :8], d[21:17], d[30:26], d35 pck1b_t ck_t: sdrams d[25:22], d[34:31] pck1a_t ck_t: sdrams d[21:18], d[30:26], d35 pck1b_c ck_c: sdrams d[25:22], d[34:31] pck1a_c ck_c: sdrams d[21:18], d[30:26], d35 l l ck1_t ck1_c 120 ? s2_n s3_n 120 ?
rev. 1.0 / aug. 2012 22 absolute maximum ratings absolute maximum dc ratings notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rat - ing conditions for extended pe riods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. ? dram component operat ing temperature range notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for mea - surement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specificatio ns will be supported. dur - ing operation, the dram case temperature must be maintained between 0 - 85 o c under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a. refresh commands must be doubled in frequency, theref ore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refres h (trefi to 7.8s) in the extended temperature range. please refer to the dimm spd for option availability b. if self-refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b).ddr3 sdrams support auto self-refresh and in extended temperature range and pl ease refer to component datasheet and/or the dimm spd for trefi requirements in the extended temperature range absolute maximum dc ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.80 v v 1,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.80 v v 1,3 v in , v out voltage on any pin relative to vss - 0.4 v ~ 1.80 v v 1 t stg storage temperature -55 to +100 o c1, 2 temperature range symbol parameter rating units notes t oper normal operating temperature range 0 to 85 o c 1,2 extended temperature range 85 to 95 o c1,3
rev. 1.0 / aug. 2012 23 ac & dc operating conditions recommended dc operating conditions notes: 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters ar e measured with vdd and vddq tied together. recommended dc operating conditions symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2
rev. 1.0 / aug. 2012 24 ac & dc input measurement levels ac and dc logic input levels for single-ended signals ac and dc input levels for single -ended command and address signals notes: 1. for input only pins except reset , vref = vrefca (dc). 2. refer to "overshoot and undershoot specifications" on page 37. 3. the ac peak noise on v ref may not allow v ref to deviate from v refca(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. 5. vih(dc) is used as a simplified symbol for vih.ca(dc100) 6. vil(dc) is used as a simp lified symbol for vil.ca(dc100) 7. vih(ac) is used as simplified symbol for vih.ca(ac175), vih.ca(ac150), vih.ca(ac135), and vih.ca(ac125); vih.ca(ac175) value is used when vref + 0.175v is referenced, vih.ca(ac150) value is used when vref + 0.150v is referenced, vih.ca(ac135) value is used when vref + 0.135v is referenced, and vih.ca(ac125) value is used when vref + 0.125v is referenced. 8. vil(ac) is used as simplified symbol fo r vil.ca(ac175), vil.ca(ac150), vil.ca(ac135), and vil.ca(ac125); vil.ca(ac175) value is used when vr ef - 0.175v is referenced, vil.ca(ac150) value is used when vref - 0.150v is referenced, vil.ca(ac135) value is used when vref - 0.135v is referenced, and vil.ca(ac125) value is used when vref - 0.125v is referenced. single ended ac and dc input levels for command and address symbol parameter ddr3-800/1066/1333/1600 ddr3-1866 unit notes min max min max vih.ca(dc100) dc input logic high vref + 0.100 vdd vref + 0.100 vdd v 1, 5 vil.ca(dc100) dc input logic low vss vref - 0.100 vss vref - 0.100 v 1, 6 vih.ca(ac175) ac input logic high vref + 0.175 note2 - - v 1, 2, 7 vil.ca(ac175) ac input logic low note2 vref - 0.175 - - v 1, 2, 8 vih.ca(ac150) ac input logic high vref + 0.150 note2 - - v 1, 2, 7 vil.ca(ac150) ac input logic low note2 vref - 0.150 - - v 1, 2, 8 vih.ca(ac135) ac input logic high - - vref + 0.135 note2 v 1, 2, 7 vil.ca(ac135) ac input logic low - - note2 vref - 0.135 v 1, 2, 8 vih.ca(ac125) ac input logic high - - vref + 0.125 note2 v 1, 2, 7 vil.ca(ac125) ac input logic low - - note2 vref - 0.125 v 1, 2, 8 v refca(dc ) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3, 4
rev. 1.0 / aug. 2012 25 ac and dc input levels for single-ended signals ddr3 sdram will support two vih/v il ac levels for ddr3-800 and ddr3-1066 as specified in the table below. ddr3 sdram will also support corresponding tds values (table 41 and table 47 in ? ddr3 device operation?) as well as derating tables in table 44 of ?ddr3 device operation? de pending on vih/vil ac lev- els. notes: 1. vref = vrefdq (dc). 2. refer to "overshoot and undershoot specifications" on page 37. 3. the ac peak noise on v ref may not allow v ref to deviate from v refdq(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. 5. vih(dc) is used as a simp lified symbol for vih.dq(dc100) 6. vil(dc) is used as a simp lified symbol for vil.dq(dc100) 7. vih(ac) is used as simplified symbol fo r vih.dq(ac175), vih.dq(ac150), and vih.dq(ac135); vih.dq(ac175) value is used when vref + 0.175v is referenced, vih.dq(ac150) value is used when vref + 0.150v is referenced, and vih.dq(ac135) value is used when vref + 0.135v is referenced. 8. vil(ac) is used as simplified symbol for vil.dq(ac175), vil.dq(ac150), and vil.dq(ac135); vil.dq(ac175) value is used when vref - 0.175v is re ferenced, vil.dq(ac150) value is used when vref - 0.150v is referenced, and vil.dq(ac135) value is used when vref - 0.135v is referenced. single ended ac and dc input levels for dq and dm symbol parameter ddr3-800/1066 ddr3-1333/1600 ddr3-1866 unit notes min max min max min max vih.dq(dc100) dc input logic high vref + 0.10 0 vdd vref + 0.100 vdd vref + 0.100 vdd v 1, 5 vil.dq(dc100) dc input logic low vss vref - 0.100 vss vref - 0.100 vss vref - 0.100 v 1, 6 vih.dq(ac175) ac input logic high vref + 0.175 note2 - - - - v 1, 2, 7 vil.dq(ac175) ac input logic low n ote2 vref - 0.175 - - - - v 1, 2, 8 vih.dq(ac150) ac input logic high vref + 0.150 not e2 vref + 0.150 note2 vref + 0.150 note2 v 1, 2, 7 vil.dq(ac150) ac input logic low n ote2 vref - 0.150 note2 vref - 0.15 0 note2 vref - 0.150 v 1, 2, 8 vih.ca(ac135) ac input logic high - - - - vref + 0.135 note2 mv 1, 2, 7 vil.ca(ac135) ac input logic low - - - - note2 vref - 0.135 mv 1, 2, 8 v refdq(dc ) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3, 4
rev. 1.0 / aug. 2012 26 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages vrefca and v refdq are illustrated in figure below. it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in the table "different ial input slew rate defini tion" on page 32. further- more v ref (t) may temporarily deviate from v ref (dc) by no more than +/- 1% vdd. illustration of v ref(dc) tolerance and v ref ac-noise limits the voltage levels for setup and hold time measurements v ih(ac) , v ih(dc) , v il(ac) , and v il(dc) are depen- dent on v ref . ?v ref ? shall be understood as v ref(dc) , as defined in figure above. this clarifies that dc-variations of v ref affect the absolute voltage a sign al has to reach to achieve a valid high or low level and therefore the time to which se tup and hold is measured. system timing and voltage budgets need to account for v ref(dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specific ation and derating values need to include time and voltage associated with v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the speci- fied limit (+/- 1% of vdd) are included in dram timings and their associated deratings. vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev. 1.0 / aug. 2012 27 ac and dc logic input levels for differential signals differential signal definition definition of differential ac-swi ng and ?time above ac-level? t dvac time differential input voltage(i.e.dqs - dqs#, ck - ck#) v il.diff.ac.max v il.diff.max 0 v il.diff.min v il.diff.ac.min t dvac half cycle t dvac
rev. 1.0 / aug. 2012 28 differential swing requirem ents for clock (ck - ck ) and strobe (dqs-dqs ) notes: 1. used to define a differential signal slew-rate. 2. for ck - ck use vih/vil (ac) of aadd/cmd and vrefca; for dqs - dqs , dqsl, dqsl , dqsu, dqsu use vih/vil (ac) of dqs and vrefdq; if a reduced ac-high or ac-low le vels is used for a signal group, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil (dc) min) for sing le-ended signals as well as the limita - tions for overshoot and undershoot. refer to "overshoot and undershoot specifications" on page 37. note : rising input differential signal shall become equal to or greater than vi hdiff(ac) level and falling input differential signal shall become equal to or less than vil(ac) level. differential ac and dc input levels symbol parameter ddr3-800, 1066, 1333, 1600 unit notes min max vihdiff differential input high + 0.200 note 3 v 1 vildiff differential input logic low note 3 - 0.200 v 1 vihdiff (ac) differential input high ac 2 x (vih (ac) - vref) note 3 v 2 vildiff (ac) differential input low ac note 3 2 x (vil (ac) - vref) v 2 allowed time before ringback (tdvac) for ck - ck and dqs - dqs ddr3-800/1066/1333/1600 ddr3-1866 slew rate [v/ns] tdvac [ps] @ vih/ldiff (ac) = 350mv tdvac [ps] @ vih/ldiff (ac) = 300mv tdvac [ps] @ vih/ldiff (ac) = 270mv (dqs-dqs )only (optional) tdvac [ps] @ vih/ldiff (ac| = 270mv min max min max min max min max > 4.0 75 - 175 - 214 - 134 - 4.0 57 -170-214-134- 3.0 50 - 167 - 191 - 112 - 2.0 38 - 119 146 67 1.8 34 - 102 - 131 - 52 - 1.6 29 - 81 - 113 - 33 - 1.4 22-54-88- 9 - 1.2 note - 19 - 56 - note - 1.0 note - note - 11 - note - < 1.0 note - note - note - note -
rev. 1.0 / aug. 2012 29 single-ended requirements for differential signals each individual component of a differen tial signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , of dqsu ) has also to comply with certain requ irements for single-ended signals. ck and ck have to approximately reach vsehmin / vselmax (approximately equal to the ac-levels (vih (ac) / vil (ac)) for add/cmd signals) in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach vsehmin / vselmax (a pproximately the ac-levels (vih (ac) / vil (ac)) for dq signals) in every half-cyc le preceding and following a valid transition. note that the applicable ac-levels for add/cmd and dq ?s might be different per speed-bin etc. e.g., if vih.ca(ac150)/vil.ca(ac150) is used for add/cmd signal s, then these ac-levels apply also for the single- ended signals ck and ck . single-ended requirements for differential signals. note that, while add/cmd and dq signal requirements are with respect to vref, the single-ended compo- nents of differential signals have a requirement with respect to vdd / 2; this is nominally the same. the transition of single-ended signals through the ac-lev els is used to measure se tup time. for single-ended components of differential signals the requirement to reach vselmax, vsehmin ha s no bearing on timing, but adds a restriction on the common mode characteristics of these signals. vdd or vddq vsehmin vdd/2 or vddq/2 vseh vselmax vss or vssq ck or dqs vsel time
rev. 1.0 / aug. 2012 30 notes: 1. for ck, ck use vih/vil (ac) of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use vih/vil (ac) of dqs. 2. vih (ac)/vil (ac) for dqs is based on vrefdq; vih (ac) /vil (ac) for add/cmd is based on vrefca; if a reduced ac-high or ac-low level is used for a signal gr oup, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil (dc) min) for sing le-ended signals as well as the limita - tions for overshoot and undershoot. refer to "overshoot and undershoot specifications" on page 37. single-ended levels for ck, dqs, dqsl, dqsu, ck , dqs , dqsl or dqsu symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max vseh single-ended high level for strobes (vdd / 2) + 0.175 note 3 v 1,2 single-ended high level for ck, ck (vdd /2) + 0.175 note 3 v 1,2 vsel single-ended low level for strobes note 3 (vdd / 2) = 0.175 v 1,2 single-ended low level for ck, ck note 3 (vdd / 2) = 0.175 v 1,2
rev. 1.0 / aug. 2012 31 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in table below. the differential input cross point voltage vix is measured from the actual cross point of true and complement signal s to the midlevel between of vdd and vss vix definition notes: 1. extended range for v ix is only allowed for clock and if sing le-ended clock input signals ck and ck are monotonic with a single-ended swing vsel / vseh of at least vdd/2 +/-250 mv, and when the differential slew rate of ck - ck is larger than 3 v/ns. ? refer to the table "single-ended levels for ck, dqs, dqsl, dqsu, ck, dqs, dqsl or dqsu" on page 30 for vsel and vseh standard values. 2. the relation between vix min/max and vsel/vseh should satisfy following. ? (vdd/2) + vix (min) - vsel ? 25mv ? vseh - ((vdd/2) + vix (max)) ? 25mv cross point voltage for differential input signals (ck, dqs) symbol parameter ddr3-800, 1066, 1333, 1600, 1866 unit notes min max v ix differential input cross point voltage relative to vdd/2 for ck, ck -150 150 mv 2 -175 175 mv 1 v ix differential input cross point voltage relative to vdd/2 for dqs, dqs -150 150 mv 2
rev. 1.0 / aug. 2012 32 slew rate definitions for single-ended input signals see 7.5 ?address / command setup, hold and derating ? on page 137 in ?ddr3 device operation? for sin- gle-ended slew rate definitions for address and command signals. ? see 7.6 ?data setup, hold and slew rate derating? on page 144 in ?ddr3 device operation? for single- ended slew rate definition for data signals. slew rate definitions for differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measur ed as shown in table and figure below. notes: the differential signal (i.e. ck-ck and dqs-dqs ) must be linear between these thresholds. differential input slew rate definition for dqs, dqs and ck, ck differential input slew rate definition description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs ) vildiffmax vihdiffmin [vihdiffmi n-vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) vihdiffmin vildiffmax [vihdiffmi n-vildiffmax] / deltatfdiff delta tfdiff delta trdiff vihdiffmin vildiffmax 0 differential input voltag e (i.e. dqs-dqs; ck-ck) differential input slew rate definition for dqs, dqs# and ck, ck#
rev. 1.0 / aug. 2012 33 ac & dc output measurement levels single ended ac and dc output levels table below shows the output levels used for measurements of single ended signals. notes: 1. the swing of 0. 1 x v ddq is based on approximately 50% of the st atic single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq / 2. differential ac and dc output levels table below shows the output levels used for measurements of single ended signals. notes: 1. the swing of 0.2 x v ddq is based on approximately 50% of the st atic differential output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq /2 at each of the differential outputs. single-ended ac and dc output levels symbol parameter ddr3-800, 1066, 1333 , 1600 unit notes v oh(dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om(dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol(dc) dc output low measurement le vel (for iv curve linearity) 0.2 x v ddq v v oh(ac) ac output high measurement level (for output sr) v tt + 0.1 x v ddq v1 v ol(ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v1 differential ac and dc output levels symbol parameter ddr3-800, 1066, 1333 , 1600 unit notes v ohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x v ddq v1 v oldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x v ddq v1
rev. 1.0 / aug. 2012 34 single ended ou tput slew rate when the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol(ac) and v oh(ac) for single ended signals are sh own in table and figure below. notes: 1. output slew rate is verified by design and charac terisation, and may not be su bject to production test. single ended output slew rate definition description: sr; slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting note 1): in two cases, a maximum slew rate of 6v/ns applies for a single dq signal within a byte lane. case 1 is a defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are static (i.e. they stay at either high or low). case 2 is a defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane switching into the opposite direction (i.e. from low to high of high to low respectively). for the remaining dq signal switching in to the opposite direction, the regular maximum limite of 5 v/ns applies. single-ended output slew rate definition description measured defined by from to single-ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) -v ol(ac) ] / deltatrse single-ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) -v ol(ac) ] / deltatfse output slew rate (single-ended) ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 units parameter symbol min max min max min max min max min max single-ended output slew rate srqse 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 1) v/ns delta tfse delta trse voh(ac) vol(ac) v single ended output voltage(l.e.dq) single ended output slew rate definition
rev. 1.0 / aug. 2012 35 differential output slew rate with the reference load for timing measurements, output slew rate for falling an d rising edges is defined and measured between voldiff (ac) and vohdiff (ac) fo r differential signals as shown in table and figure below. differential output slew rate definition differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v oldiff (ac) v ohdiff (ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatrdiff differential output slew rate for falling edge v ohdiff (ac) v oldiff (ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatfdiff notes: 1. output slew rate is verified by design and charac terization, and may not be subject to production test. differential output slew rate ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 units parameter symbol min max min max min max min max min max differential output slew rate srqdiff 5 12 5 12 5 12 5 12 5 12 v/ns description: sr; slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting delta tfdiff delta trdiff vohdiff(ac) voldiff(ac) o differential output voltage(i.e. dqs-dqs) differential output slew rate definition
rev. 1.0 / aug. 2012 36 reference load for ac timing and output slew rate figure below represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of an y particular system environment or a depiction of the actual load presented by a production tester. system de signers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transm ission lines terminated at the tester electronics. reference load for ac timing and output slew rate dut dq dqs dqs vddq 25 ohm vtt = vddq/2 ck, ck
rev. 1.0 / aug. 2012 37 overshoot and unders hoot specifications address and control overshoot and undershoot specifications address and control overshoo t and undershoot definition ac overshoot/undershoot specification for address and control pins parameter ddr3- 800 ddr3- 1066 ddr3- 1333 ddr3- 1600 ddr3- 1866 units maximum peak amplitude allowed for overshoot area. (see figure below) 0.4 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoo t area. (see figure below) 0.4 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd (s ee figure below) 0.67 0.5 0.4 0.33 0.28 v-ns maximum undershoot area below vss (see figure below) 0.67 0.5 0.4 0.33 0.28 v-ns (a0-a15, ba0-ba3, cs , ras , cas , we , cke, odt) see figure below for each parameter definition maximum amplitude overshoot area vdd vss maxim um am plitude undershoot area time (ns) address and control overshoot and undershoot definition volts (v)
rev. 1.0 / aug. 2012 38 clock, data, strobe and mask over shoot and undershoot specifications clock, data, strobe and mask ov ershoot and undershoot definition ac overshoot/undershoot specificatio n for clock, data, strobe and mask parameter ddr3- 800 ddr3- 1066 ddr3- 1333 ddr3- 1600 ddr3- 1866 units maximum peak amplitude allowed for overshoot area. (see figure below) 0.4 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoo t area. (see figure below) 0.4 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd (see figure below) 0.25 0.19 0.15 0.13 0.11 v-ns maximum undershoot area below vss (see figure below) 0.25 0.19 0.15 0.13 0.11 v-ns (ck, ck , dq, dqs, dqs , dm) see figure below for ea ch parameter definition maximum amplitude overshoot area vddq vssq m axim um am plitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v)
rev. 1.0 / aug. 2012 39 refresh parameters by device density refresh parameters by device density parameter rtt_nom setting 512mb 1gb 2gb 4gb 8gb units notes ref command act or ref command time trfc 90 110 160 260 350 ns average periodic refresh interval trefi 0 ? c ? t case ? 85 ? c 7.8 7.8 7.8 7.8 7.8 us 85 ? c ? t case ? 95 ? c 3.9 3.9 3.9 3.9 3.9 us 1
rev. 1.0 / aug. 2012 40 standard speed bins ddr3 sdram standard speed bins include tck, trcd , trp, tras and trc for each corresponding bin. ddr3-800 speed bins for specific notes see "speed bin table notes" on page 45. speed bin ddr3-800e unit notes cl - nrcd - nrp 6-6-6 parameter symbol min max internal read command to first data t aa 15 20 ns act to internal read or write delay time t rcd 15 ? ns pre command period t rp 15 ? ns act to act or ref command period t rc 52.5 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3 supported cl settings 6 n ck supported cwl settings 5 n ck
rev. 1.0 / aug. 2012 41 ddr3-1066 speed bins for specific notes see "speed bin table notes" on page 45. speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,6 cwl = 6 t ck(avg) reserved ns 1,2,3,4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3 supported cl settings 6, 7, 8 n ck supported cwl settings 5, 6 n ck
rev. 1.0 / aug. 2012 42 ddr3-1333 speed bins for specific notes see "speed bin table notes" on page 45. speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 (13.125) 5,10 20 ns act to internal read or write delay time t rcd 13.5 (13.125) 5,10 ?ns pre command period t rp 13.5 (13.125) 5,10 ?ns act to act or ref command period t rc 49.5 (49.125) 5,10 ?ns act to pre command period t ras 36 9 * trefi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,7 (optional) 5,10 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3 (optional) ns 5 supported cl settings 6, 7, 8, 9, 10 n ck supported cwl settings 5, 6, 7 n ck
rev. 1.0 / aug. 2012 43 ddr3-1600 speed bins for specific notes see "speed bin table notes" on page 45. speed bin ddr3-1600k unit note cl - nrcd - nrp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 (13.125) 5,10 20 ns act to internal read or write delay time t rcd 13.75 (13.125) 5,10 ?ns pre command period t rp 13.75 (13.125) 5,10 ?ns act to act or ref command period t rc 48.75 (48.125) 5,10 ?ns act to pre command period t ras 35 9 * trefi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,8 cwl = 6 t ck(avg) reserved ns 1,2,3,4,8 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,8 (optional) 5,10 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4,8 (optional) 5,10 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1,2,3 supported cl settings 5, 6, 7, 8, 9, 10, 11 n ck supported cwl settings 5, 6, 7, 8 n ck
rev. 1.0 / aug. 2012 44 ddr3-1866 speed bins for specific notes see "speed bin table notes" on page 45. speed bin ddr3-1866m unit note cl - nrcd - nrp 13-13-13 parameter symbol min max internal read command to first data t aa 13.91 (13.125) 5,11 20 ns act to internal read or write delay time t rcd 13.91 (13.125) 5,11 ?ns pre command period t rp 13.91 (13.125) 5,11 ?ns act to pre command period t ras 34 9 * trefi ns act to act or pre command period t rc 47.91 (47.125) 5,11 -ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,9 cwl = 6 t ck(avg) reserved ns 1,2,3,4,9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,9 cwl = 7 t ck(avg) reserved ns 1,2,3,4,9 cwl = 8,9 t ck(avg) reserved ns 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4,9 cwl = 8 t ck(avg) reserved ns 1,2,3,4,9 cwl = 9 t ck(avg) reserved ns 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,9 cwl = 8 t ck(avg) reserved ns 1,2,3,4,9 cl = 11 cwl = 5,6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1,2,3,4,9 cwl = 9 t ck(avg) reserved ns 1,2,3,4 cl = 12 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) reserved ns 1,2,3,4 cl = 13 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1.07 <1.25 ns 1, 2, 3 supported cl settings 6, 7, 8, 9, 10, 11, 13 n ck supported cwl settings 5, 6, 7, 8, 9 n ck
rev. 1.0 / aug. 2012 45 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when mak - ing a selection of tck(avg), both need to be fulfille d: requirements from cl setting as well as require - ments from cwl setting. 2. tck(avg).min limits: since cas latency is not pure ly analog - data and strobe output are synchro - nized by the dll - all possible intermediate freque ncies may not be guaranteed. an application should use the next smaller jedec standard tck(avg) valu e (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat - ing cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next ?supported cl?, where tck(avg) = 3.0 ns should only be used for cl = 5 calculation. 3. tck(avg).max limits: calculate tck(avg) = taa.ma x / cl selected and round the resulting tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to cl selected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the indust ry to support this setting, however, it is not a man - datory feature. refer to dimm data sheet and/or th e dimm spd information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 7. any ddr3-1333 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 8. any ddr3-1600 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production test s but verified by desi gn/characterization. 9. any ddr3-1866 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 10. ddr3 sdram devices supporting optional down binni ng to cl=7 and cl=9, and taa/trcd/trp must be 13.125 ns or lower. spd settings must be programmed to match. for example, ddr3-1333h devices supporting down binning to ddr3-1066f shou ld program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20) . ddr3-1600k devices supporting down binning to ddr3-1333h or ddr3-1600f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be programmed accordingly. for ex ample, 49.125ns (trasmin + trpmin = 36 ns + 13.125 ns) for ddr3-1333h and 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3-1600k. 11. ddr3 sdram devices supporting opti onal down binning to cl=11, cl=9 and cl=7, taa/trcd/trpmin must be 13.125ns. spd setting must be programe d to match. for example, ddr3-1866 devices sup - porting down binning to ddr3-1600 or ddr3-1333 or 1066 should program 13.125ns in spd bytes for taamin(byte 16), trcdmin(byte 18) and trpmin(byte 20) is programmed to 13.125ns, trcmin(byte 21,23) also should be programmed accordingly. fo r example, 47.125ns (trasmin + trpmin = 34ns + 13.125ns)
rev. 1.0 / aug. 2012 46 environmental parameters note : 1. stress greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functional operation at or above the condit ions indicated is not implied. expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. up to 9850 ft. 3. the designer must meet the case temperature specifications for individual module components. symbol parameter rating units notes t opr operating temperature see note 3 h opr operating humidity (relative) 10 to 90 % 1 t stg storage temperature -50 to +100 o c 1 h stg storage humidity (without condensation) 5 to 95 % 1 p bar barometric pressure (operating & storage) 105 to 69 k pascal 1, 2
rev. 1.0 / aug. 2012 47 idd and iddq specification pa rameters and test conditions idd and iddq measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patt erns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt , idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et and idd7) are measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied toge ther. any idd current is not included in iddq cur - rents. ? attention: iddq values cannot be directly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io power to actual io po wer as outlined in figure 2. in dram module application, iddq cannot be measured separately si nce vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?mid_level? is defined as inputs are vref = vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1. ? basic idd and iddq measurement co nditions are described in table 2. ? detailed idd and iddq measurement-loop patte rns are described in table 3 through table 10. ? idd measurements are done after properly initializi ng the ddr3 sdram. this includes but is not lim - ited to setting ? ron = rzq/7 (34 ohm in mr1); ? qoff = 0 b (output buffer enabled in mr1); ? rtt_nom = rzq/6 (40 ohm in mr1); ? rtt_wr = rzq/2 (120 ohm in mr2); ? tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ? define d = { cs , ras , cas , we }:= {high, low, low, low} ? define d = { cs , ras , cas , we }:= {high, high, high, high}
rev. 1.0 / aug. 2012 48 figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above figure 2 - correlation from simulated channel io power to actual ch annel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 1.0 / aug. 2012 49 table 1 -timings used for idd an d iddq measurement-loop patterns table 2 -basic idd and id dq measurement conditions symbol ddr3-1333 ddr3-1600 ddr3-1866 unit 9-9-9 11-11-11 13-13-13 t ck 1.5 1.25 1.07 ns cl 9 11 13 nck n rcd 91113nck n rc 33 39 45 nck n ras 24 28 32 nck n rp 91113nck n faw 1kb page size 20 24 26 nck 2kb page size 30 32 33 nck n rrd 1kb page size 4 5 5 nck 2kb page size 5 6 6 nck n rfc -512mb 60 72 85 nck n rfc -1 gb 74 88 103 nck n rfc - 2 gb 107 128 150 nck n rfc - 4 gb 174 208 243 nck n rfc - 8 gb 234 280 328 nck symbol description i dd0 operating one bank active-precharge current ? cke: high; external clock: on; tck, nrc, nras, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: partiall y toggling according to table 3; data io: mid-level; dm: stable at 0; bank activity: cyclin g with one bank active at a time: 0, 0,1,1,2,2,... (see table 3); output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3. i dd1 operating one bank active-precharge current cke: high; external clock: on; tck, n rc, nras, nrcd, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, da ta io: partially toggling ac cording to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4.
rev. 1.0 / aug. 2012 50 i dd2n precharge standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd2nt precharge standby odt current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 6; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6; pattern details: see table 6. i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0; prec harge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0; prec harge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rt t: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 symbol description
rev. 1.0 / aug. 2012 51 i dd4r operating burst read current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling according to tabl e 7; data io: seamless read data burst with different data between one burst and the next one according to tabl e 7; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,...(see table 7); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd4w operating burst write current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling according to tabl e 8; data io: seamless read data burst with different data between one burst and the next one according to tabl e 8; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...(see table 8); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8. i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank address inputs: partiall y toggling according to table 9; data io: mid_level; dm: stable at 0; bank activity: ref command every nref (see table 9); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd6et self-refresh current: extended temperature range (optional) t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extended e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level symbol description
rev. 1.0 / aug. 2012 52 a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nr as, nrcd, nrrd, nfaw, cl: see table 1; bl: 8 a),f) ; al: cl-1; cs : high between act and rda; command, address, bank a ddress inputs: partially togg ling according to table 10; data io: read data burst with different data betw een one burst and the next one according to table 10; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,.. .7) with different address- ing, wee table 10; output buffer an d rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10. symbol description
rev. 1.0 / aug. 2012 53 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1111 0 0000 0 f 0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 1.0 / aug. 2012 54 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid- level. b) burst sequence driven on each dq signal by re ad command. outside burst operation, dq signals are mid_level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act001100000000 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 111100000000 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre001000000000 - ... repeat pattern 1...4 until nr c - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111000000f0 - ... repeat pattern nrc + 1,. ..4 until nrc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1, ...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1, ...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 1.0 / aug. 2012 55 table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 111 1 0 0 0 0 0 f 0 - 3d 111 1 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 1.0 / aug. 2012 56 table 7 - idd4r and iddq4r measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. b) burst sequence driven on each dq signal by write co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 1.0 / aug. 2012 57 table 9 - idd5b measur ement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 1.0 / aug. 2012 58 table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2 d 1 0 0 0 0 0 00 0 0 0 0 - ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd d 1 0 0 0 0 3 00 0 0 f 0 - assert and repeat abov e d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 f 0 - assert and repeat abov e d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d 1 0 0 0 0 0 00 0 0 f 0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+2 d 1 0 0 0 0 1 00 0 0 0 0 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d 1 0 0 0 0 3 00 0 0 0 0 - assert and repeat abov e d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 0 0 - assert and repeat abov e d command until 4* nfaw - 1, if necessary
rev. 1.0 / aug. 2012 59 idd specifications (tcase: 0 to 95 o c) *module idd values in the datasheet are only a calcul ation based on the component idd spec and register power. the actual measurements may vary according to dq loading cap. 2gb, 256m x 72 r-di mm: hmt325v7cfr8c 4gb, 512m x 72 r-di mm: hmt351v7cfr8c symbol ddr3 1333 ddr3 1600 ddr3 1866 unit note idd0 1124 1169 1169 ma idd1 1214 1259 1304 ma idd2n 944 989 989 ma idd2nt 989 1034 1034 ma idd2p0 336 336 336 ma idd2p1 363 363 381 ma idd2q 971 971 989 ma idd3n 1007 1034 1034 ma idd3p 363 381 390 ma idd4r 1574 1709 1889 ma idd4w 1529 1619 1844 ma idd5b 1799 1844 1844 ma idd6 336 336 336 ma idd6et 354 354 354 ma idd7 2384 2429 2564 ma symbol ddr3 1333 ddr3 1600 ddr3 1866 unit note idd0 1304 1439 1439 ma idd1 1394 1529 1574 ma idd2n 1124 1214 1214 ma idd2nt 1214 1304 1304 ma idd2p0 444 444 444 ma idd2p1 498 498 534 ma idd2q 1178 1178 1214 ma idd3n 1250 1304 1304 ma idd3p 498 534 552 ma idd4r 1754 1979 2159 ma idd4w 1709 1889 2114 ma idd5b 1979 2114 2114 ma idd6 444 444 444 ma idd6et 480 480 480 ma idd7 2564 2699 2834 ma
rev. 1.0 / aug. 2012 60 4gb, 512m x 72 r-di mm: hmt351v7cfr4c 8gb, 1g x 72 r-di mm: hmt41gv7cmr8c symbol ddr3 1333 ddr3 1600 ddr3 1866 unit note idd0 1484 1574 1574 ma idd1 1664 1754 1844 ma idd2n 1124 1214 1214 ma idd2nt 1214 1304 1304 ma idd2p0 444 444 444 ma idd2p1 498 498 534 ma idd2q 1178 1178 1214 ma idd3n 1250 1304 1304 ma idd3p 498 534 552 ma idd4r 2384 2654 3014 ma idd4w 2294 2474 2924 ma idd5b 2834 2924 2924 ma idd6 444 444 444 ma idd6et 480 480 480 ma idd7 4004 4094 4364 ma symbol ddr3 1333 ddr3 1600 unit note idd0 1664 1979 ma idd1 1754 2069 ma idd2n 1484 1664 ma idd2nt 1664 1844 ma idd2p0 660 660 ma idd2p1 768 768 ma idd2q 1592 1592 ma idd3n 1736 1844 ma idd3p 768 840 ma idd4r 2114 2519 ma idd4w 2069 2429 ma idd5b 2339 2654 ma idd6 660 660 ma idd6et 732 732 ma idd7 2924 3239 ma
rev. 1.0 / aug. 2012 61 8gb, 1g x 72 r-di mm: hmt41gv7cmr4c symbol ddr3 1333 ddr3 1600 unit note idd0 1844 2114 ma idd1 2024 2294 ma idd2n 1484 1664 ma idd2nt 1664 1844 ma idd2p0 660 660 ma idd2p1 768 768 ma idd2q 1592 1592 ma idd3n 1736 1844 ma idd3p 768 840 ma idd4r 2744 3194 ma idd4w 2654 3014 ma idd5b 3194 3464 ma idd6 660 660 ma idd6et 732 732 ma idd7 4364 4634 ma
rev. 1.0 / aug. 2012 62 module dimensions 256mx72 - hmt325v7cfr8c 5.175 detail a detail b 2.10 0.15 47.00 71.00 2x3.0 0.10 front 1 3 0.1 15.80 0.1 back 0.35 2.50 0.20 1.00 0.80 0.05 detail of contacts a 1.50 0.10 detail of contacts b 0.3 0.15 0.3~0.1 5.00 3.80 2.50 2.50 0.20 registering spd/ts clock driver 3 0.1 128.95 133.35 13.60 14.90 0.4 13.60 14.90 detail of contacts c 1.27 010 mm max 3.65mm max side 8.00 0.1 18.75 0.15 detail c 120 121 240 note : 1. tolerance on all dimensions unless otherwise stated. 0.13 ? units: millimeters 0.05 2x r0.75 max
rev. 1.0 / aug. 2012 63 512mx72 - hmt351v7cfr8c 5.175 detail a detail b 2.10 0.15 47.00 71.00 2x3.0 0.10 front 1 3 0.1 15.80 0.1 back 1.50 0.10 detail of contacts b 0.3 0.15 0.3~0.1 5.00 3.80 2.50 2.50 0.20 registering spd/ts clock driver 3 0.1 128.95 133.35 13.60 14.90 0.4 13.60 14.90 detail of contacts c 1.27 010 mm max 3.65mm max side 8.00 0.1 18.75 0.15 detail c 120 121 240 note : 1. tolerance on all dimensions unless otherwise stated. 0.13 ? units: millimeters 0.35 2.50 0.20 1.00 0.80 0.05 detail of contacts a 0.05 2x r0.75 max
rev. 1.0 / aug. 2012 64 512mx72 - hmt351v7cfr4c 5.175 detail a detail b 2.10 0.15 47.00 71.00 2x3.0 0.10 front 1 3 0.1 15.80 0.1 back 1.50 0.10 detail of contacts b 0.3 0.15 0.3~0.1 5.00 3.80 2.50 2.50 0.20 registering spd/ts clock driver 3 0.1 128.95 133.35 13.60 14.90 0.4 13.60 14.90 detail of contacts c 1.27 010 mm max 3.65mm max side 8.00 0.1 18.75 0.15 detail c 120 121 240 note : 1. tolerance on all dimensions unless otherwise stated. 0.13 ? units: millimeters 0.35 2.50 0.20 1.00 0.80 0.05 detail of contacts a 0.05 2x r0.75 max
rev. 1.0 / aug. 2012 65 1gx72 - hmt41gv7cmr8c 5.175 detail a detail b 2.10 0.15 47.00 71.00 2x3.0 0.10 front 1 3 0.1 15.80 0.1 back 1.50 0.10 detail of contacts b 0.3 0.15 0.3~0.1 5.00 3.80 2.50 2.50 0.20 registering spd/ts clock driver 3 0.1 128.95 133.35 13.60 14.90 0.4 13.60 14.90 detail of contacts c 1.27 010 mm max 3.65mm max side 8.00 0.1 18.75 0.15 detail c 120 121 240 note : 1. tolerance on all dimensions unless otherwise stated. 0.13 ? units: millimeters 0.35 2.50 0.20 1.00 0.80 0.05 detail of contacts a 0.05 2x r0.75 max ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp
rev. 1.0 / aug. 2012 66 1gx72 - hmt41gv7cmr8 c - heat spreader 1.50 0.10 detail of contacts b 0.3 0.15 0.3~1.0 5.00 3.80 2.50 2.50 0.20 0.4 8.5 9.8 detail of contacts c 1.27 010 mm max 7.55mm max side spd/ts 1 ddp ddp ddp ddp ddp ddp ddp ddp ddp 120 6.2mm 29 29 127 12.3 13.3 18.75 0.15 spd/ts 121 ddp ddp ddp ddp ddp ddp ddp ddp ddp 240 front back note : 1. tolerance on all dimensions unless otherwise stated. 2.in order to uninstall fdhs, pl ease contact sales administrator. 0.13 ? units: millimeters 0.35 2.50 0.20 1.00 0.80 0.05 detail of contacts a 0.05
rev. 1.0 / aug. 2012 67 1gx72 - hmt41gv7cmr4c 5.175 detail a detail b 2.10 0.15 47.00 71.00 2x3.0 0.10 front 1 3 0.1 15.80 0.1 back 1.50 0.10 detail of contacts b 0.3 0.15 0.3~0.1 5.00 3.80 2.50 2.50 0.20 registering spd/ts clock driver 3 0.1 128.95 133.35 13.60 14.90 0.4 13.60 14.90 detail of contacts c 1.27 010 mm max 3.65mm max side 8.00 0.1 18.75 0.15 detail c 120 121 240 note : 1. tolerance on all dimensions unless otherwise stated. 0.13 ? units: millimeters 0.35 2.50 0.20 1.00 0.80 0.05 detail of contacts a 0.05 2x r0.75 max ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp ddp
rev. 1.0 / aug. 2012 68 1gx72 - hmt41gv7cmr4 c - heat spreader 1.50 0.10 detail of contacts b 0.3 0.15 0.3~1.0 5.00 3.80 2.50 2.50 0.20 0.4 8.5 9.8 detail of contacts c 1.27 010 mm max 7.55mm max side spd/ts 1 ddp ddp ddp ddp ddp ddp ddp ddp ddp 120 6.2mm 29 29 127 12.3 13.3 18.75 0.15 spd/ts 121 ddp ddp ddp ddp ddp ddp ddp ddp ddp 240 front back note : 1. tolerance on all dimensions unless otherwise stated. 2.in order to uninstall fdhs, pl ease contact sales administrator. 0.13 ? units: millimeters 0.35 2.50 0.20 1.00 0.80 0.05 detail of contacts a 0.05

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